In general, a technique is known in which, by analyzing delays that occur between flip-flops (which will be referred to as “FFs” hereafter) included in the LSI (Large Scale Integrated circuit), the manufacturing yield of an LSI as a whole is estimated with respect to an operating frequency according to the delay.
Here, the aforementioned operating frequency can be calculated by calculating the inverse of the delay.
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Japanese Laid-open Patent Publication No. 2004-252831.
[Patent Document 2]
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[Non-Patent Document 1]
Akio Miyoshi, Toshihiko Yokota, “method for reducing irregularities in 65 nm in IBM”, Nikkei Microdevices (February issue), pp. 53-59, 2007.
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A Nardi, E. Tuncer, et al, “Use of Statistical Timing Analysis on Real Designs”, Design Automation and Test in Europe, 2007.
Furthermore, as a method for estimating the manufacturing yield of an LSI as a whole, static timing analysis using an STA (static timing analysis) and statistical timing analysis using an SSTA (statistical static timing analysis) are known, for example.
Static timing analysis using an STA is a method in which a predetermined delay is applied to each gate which is a logic element such as a logical AND circuit (AND circuit), a logical OR circuit (OR circuit), or the like, which is a component of the LSI, and to each net which is a wiring line that connects the gates, and the delays thus applied to the gates and the nets arranged on the paths between the FFs are added, following which the sum thus calculated is multiplied by a predetermined scattering coefficient corresponding to the semiconductor technology used to manufacture the LSI, thereby calculating the delay that occurs on each path between FFs.
On the other hand, statistical timing analysis using an SSTA is a method in which a delay distribution is applied to each gate which is a logic element and which is a component of the LSI, and to each net, and the delay distributions thus applied to the gates and the nets arranged on the paths between FFs are statistically added, thereby obtaining a probability density function for each path between the FFs. Furthermore, the probability density function for the LSI as a whole is obtained by performing a statistical maximum computation on the probability density functions for all the paths between FFs comprising the LSI. Moreover, the cumulative distribution function for the LSI as a whole is obtained by integrating the probability density function for the LSI as a whole. The cumulative distribution function thus obtained represents the yield of the entire LSI with respect to a frequency. Thus, by obtaining the cumulative distribution function, such an arrangement is capable of estimating the manufacturing yield of the LSI.
The aforementioned static timing analysis using an. STA has the advantage of allowing the calculation to be executed with high speed as compared with statistical timing analysis using an SSTA. However, the static timing analysis using an STA is not capable of providing a value closer to the actual value than that provided by the statistical timing analysis using an SSTA, leading to poor precision in the timing analysis.
On the other hand, the aforementioned statistical timing analysis using an SSTA is capable of providing a value closer to an actual value than that provided by the static timing analysis using an STA. However, such an arrangement can execute processing such as addition of the delay distributions with respect to the gates and nets for each path between the FFs, leading to long processing time. Furthermore, in order to improve the calculation precision of the statistical timing analysis using an SSTA, there is a need to increase the number of data points in the delay distributions with respect to the gates and nets for each path between the FFs. However, such an arrangement requires a large amount of execution memory.
Accordingly, it is not practical to apply the statistical timing analysis using an SSTA to all the paths between the FFs that form a large-scale LSI such as multi-core processors or the like having multiple computation cores, which have been put to practical use in recent years.